Silicon Labs /EFR32ZG23B020F512IM40 /PFMXPPRF_S /RFIMDCDCCTRL1

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Interpret as RFIMDCDCCTRL1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DCDCDIVEN)DCDCDIVEN 0 (DCDCDIVINVEN)DCDCDIVINVEN 0 (DIVRATIO8)DCDCDIVRATIO

DCDCDIVRATIO=DIVRATIO8

Description

No Description

Fields

DCDCDIVEN

DCDC DIV Enable

DCDCDIVINVEN

DCDC DIV Inverter Enable

DCDCDIVRATIO

DCDC DIV Ratio

0 (DIVRATIO8): Dividing master_rf clk by 8, D=50%

1 (DIVRATIO9): Dividing master_rf clk by 9, D=44.4%

2 (DIVRATIO10): Dividing master_rf clk by 10, D=40%

3 (DIVRATIO11): Dividing master_rf clk by 11, D=36.4%

4 (DIVRATIO12): Dividing master_rf clk by 12, D=50%

5 (DIVRATIO13): Dividing master_rf clk by 13, D=46.2%

6 (DIVRATIO14): Dividing master_rf clk by 14, D=42.9%

7 (DIVRATIO15): Dividing master_rf clk by 15, D=40%

8 (DIVRATIO16): Dividing master_rf clk by 16, D=50%

9 (DIVRATIO17): Dividing master_rf clk by 17, D=47.1%

10 (DIVRATIO18): Dividing master_rf clk by 18, D=44.4%

11 (DIVRATIO19): Dividing master_rf clk by 19, D=42.1%

12 (DIVRATIO20): Dividing master_rf clk by 20, D=60%

13 (DIVRATIO21): Dividing master_rf clk by 21, D=57.1%

14 (DIVRATIO22): Dividing master_rf clk by 22, D=54.5%

15 (DIVRATIO23): Dividing master_rf clk by 23, D=52.2%

Links

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